Switching power supply capable of ac to dc conversion

ABSTRACT

A switching power supply capable of translating a.c. voltage of sinusoidal waveform into d.c. voltage, comprising a rectifier circuit connected to a pair of a.c. input terminals for rectifying the incoming commercial a.c. voltage. A first main switch is connected between the pair of outputs of the rectifier circuit via a main inductor. A smoothing capacitor is connected in parallel with the first main switch via a rectifying diode. A second main switch is connected in parallel with the smoothing capacitor via the primary winding of a transformer. The first and the second main switch are each provided with a soft-switching capacitor connected in parallel therewith. A first and a second ancillary inductor, electromagnetically coupled respectively to the main inductor and to the transformer primary, are connected in parallel with the first and the second soft-switching capacitor, respectively, via an ancillary switch. A switch control circuit is connected to the main switches for on-off control thereof at a repetition frequency higher than the frequency of the input a.c. voltage, and to the ancillary switch for on-off control thereof at such a repetition frequency, and with such conducting periods, as to assure soft turn-on of the main switches.

BACKGROUND OF THE INVENTION

This invention relates to electric power supplies, and particularly to aswitching power supply capable of a.c.-to-d.c. voltage conversion,featuring provisions for attainment of closer approximation of the inputcurrent waveform to a sinusoidal wave, and for that of a higher powerfactor, than by the comparable prior art.

The switching power supply or voltage regulator has long been familiarwhich comprises a rectifying and smoothing circuit to be coupled to asource of a.c. power, and a d.c.-to-d.c. converter circuit connected tothe rectifying and smoothing circuit. The rectifying and smoothingcircuit comprises a rectifier circuit and a smoothing capacitor.Although so simple in configuration, this known rectifying and smoothingcircuit possesses the disadvantage of a somewhat poor power factor as aresult of the fact that the smoothing capacitor is charged only at oradjacent the peaks of the a.c. voltage of sinusoidal waveform. Anotherdrawback is that the input current is not favorable in waveform.

Designed to defeat these shortcomings, a more advanced switching powersupply has also been suggested which comprises an inductor connectedbetween the rectifier circuit and the smoothing capacitor, and a switchwhich is connected between the pair of outputs of the rectifier circuitand which is controllable via the inductor. The smoothing capacitor isconnected in parallel with the switch via the rectifying diode. Thisknown circuit comprising the inductor and the switch is sometimesreferred to as the step-up power-factor improvement circuit. As theswitch is turned on and off at a repetition frequency higher than thefrequency of the input a.c. voltage, the current flowing through theinductor has a peak value in proportion with the instantaneous value ofthe input voltage. The results are a close approximation of the inputcurrent waveform to a sinusoidal waveform, and an improvement in powerfactor. It is also possible to make the voltage across the smoothingcapacitor higher than the maximum value of the a.c. voltage.

Offsetting these advantages of the prior art device is the fact thatswitching losses occur both at the switch included in the step-uppower-factor improvement circuit and at that in the d.c.-to-d.c.converter circuit connected thereto, resulting in a substantial decreasein efficiency. It must also be taken into consideration that the on-offcontrol of the power-factor improvement circuit switch and d.c.-to-d.c.converter circuit switch at different repetition frequencies isundesirable. Noise was indeed easy to be produced according to thisswitch-driving scheme, and the switches prone to become unstable inoperation, as a result of the mutual interference of the differentdriving frequencies of both switches.

Japanese Unexamined Patent Publication No. 8-154379 suggests a differenttype of switching power supply. The switch in the d.c.-to-d.c. convertercircuit is utilized for switching both the d.c. voltage across thesmoothing capacitor and the current through the inductor for powerfactor improvement. One switch performs the dual purpose of power factorimprovement and d.c.-to-d.c. conversion, but to lesser extents than bytwo switches.

SUMMARY OF THE INVENTION

The present invention has it among its objects, in a switching powersupply of the type defined, to further improve the power factor and, atthe same time, to most effectively and inexpensively lessen power lossesdue to the switch included in the power-factor improvement circuit andthat in the d.c.-to-d.c. converter.

Briefly, the present invention may be summarized as a switching powersupply capable of translating a.c. voltage of sinusoidal waveform intod.c. voltage. Included is a rectifier circuit connected to a pair ofinput terminals for rectifying the input a.c. voltage, the rectifiercircuit having a first and a second output for providing a rectifieroutput voltage. A first main switch is connected to the first output ofthe rectifier circuit via a main inductor on one hand and, on the otherhand, to the second output of the rectifier circuit. The first mainswitch has capacitance means for its soft switching, the capacitancemeans being in the form of either a discrete capacitor connected inparallel therewith or its parasitic capacitance. A rectifying diode isconnected to the rectifier circuit via the main inductor. A smoothingcapacitor is connected in parallel with the main switch via therectifying diode. A transformer is provided which has a primary windingthrough which a second main switch is connected in parallel with thesmoothing capacitor. The second main switch has its own soft-switchingcapacitance means. A rectifying and smoothing circuit is connected tothe transformer for providing output d.c. voltage. A first ancillaryinductor is connected to the main inductor and electromagneticallycoupled thereto. An ancillary switch is connected to the main inductorvia the first ancillary inductor on one hand and, on the other hand, tothe second output of the rectifier circuit. A first reverse-blockingdiode is connected in series with the first ancillary inductor.Electromagnetically coupled to the primary winding of the transformer, asecond ancillary inductor has one extremity connected to a junctionbetween the second main switch and the smoothing capacitor, and anotherextremity connected to the ancillary switch. A second reverse-blockingdiode is connected in series with the second ancillary inductor. Alsoincluded is a switch control circuit which is connected to the firstmain switch for on-off control thereof at a repetition frequency higherthan the frequency of the input a.c. voltage, to the second main switchfor on-off control thereof so as to cause d.c. voltage to beintermittently applied from the smoothing capacitor to the primarywinding of the transformer, and to the ancillary switch for on-offcontrol thereof at such a repetition frequency, and with such conductingperiods, as to assure soft turn-on of the first and the second mainswitch.

The invention as summarized above offers the following advantages:

1. The first soft-switching capacitor and the first ancillary inductorconstitute in combination a resonant circuit conducive to the softswitching of the first main switch. As a result, less power loss andless noise occur at the first main switch, and the power factor isimproved with the power loss kept at a minimum.

2. The second soft-switching capacitance means and the second ancillaryinductor constitute in combination a second resonant circuit conduciveto the soft switching of the second main switch. This second main switchis therefore also kept from power loss and noise production, andd.c.-to-d.c. conversion is accomplished with minimal power loss.

3. The first and the second resonant circuit share the ancillary switchfor soft-switching the first and the second main switch, rather thanemploying separate ancillary switches for the same purposes.

4. The electromagnetic coupling of the first ancillary inductor with themain inductor is effective to restrict the current flowing through themain inductor into the smoothing capacitor when the ancillary switch isturned on with consequent voltage application to the first ancillaryinductor. The current thus flowing into the smoothing capacitor willdrop to zero in a relatively short period of time, resulting in earlycommencement of discharge by the first soft-switching capacitance means.

5. Similarly, as a result of the electromagnetic coupling of the secondancillary inductor with the transformer primary, the energy release fromtransformer primary to rectifying and smoothing circuit is completed ina relatively short period of time when the ancillary switch is turned onwith consequent voltage application to the second ancillary inductor.The result is an early commencement of discharge by the secondsoft-switching capacitance means.

6. Electromagnetically coupled together, moreover, the main inductor andthe first ancillary inductor are manufacturable as a compact, integralcombinations.

7. The transformer primary and the second ancillary inductor arelikewise electromagnetically coupled together. The transformer ismanufacturable in compact, integral combination with the secondancillary inductor.

It is also an advantage of this invention that the two main switches areboth driven at the same switching frequency. The switch control circuitis much simpler and inexpensive in construction than if the mainswitches are driven at different frequencies. The driving of the mainswitches at different frequencies is objectionable for an additionalreason: The different driving frequencies would be difficult of creationbecause of their possible mutual interference. Noise production wouldalso be easier to occur.

In some embodiments of the invention, not only are the two main switchesdriven at the same frequency, but they are turned on simultaneously. Theswitch control circuit can then be further simplified in construction.

In some other embodiments, however, the two main switches are turned onat different moments. One such embodiment employs what are termedconducting period limitation signals for variously delaying thebeginnings of predefined tentative conducting periods of the mainswitches. The conducting period limitation signals permit the mainswitches to be turned on at different moments that are independentlyadjustable.

A yet further embodiment is disclosed in which the main switches areturned on when the voltages across them drop below predeterminedreference voltages. The main switches can then be turned on at zero orvery low voltages more positively than in cases where they are turned onat moments predetermined by timers.

The above and other objects, features and advantages of this inventionwill become more apparent, and the invention itself will best beunderstood, from a study of the following detailed description andappended claims, with reference had to the attached drawings showing thepreferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic electrical diagram of a first preferred form ofswitching power supply according to the invention;

FIG. 2 is a schematic electrical diagram, partly in block form, showingin more detail the switch control circuit included in the FIG. 1embodiment;

FIG. 3, consisting of (A) through (I), is a series of diagrams showingthe voltage and current waveforms appearing at various parts of the FIG.2 switch control circuit;

FIG. 4, consisting of (A) through (D), is a series of diagrams showingthe voltage and current waveforms appearing at various parts of the FIG.1 circuitry in order to explain how improvements in power factor andinput waveform are achieved;

FIG. 5, consisting of (A) through (O), is a series of diagrams showingthe voltage and current waveforms appearing at various parts of the FIG.1 circuitry in order to explain soft switching;

FIG. 6 is a view similar to FIG. 1 but showing a second preferred formof switching power supply according to the invention;

FIG. 7, consisting of (A) through (O), is a series of diagrams showingthe voltage and current waveforms appearing at various parts of the FIG.6 circuitry;

FIG. 8 is a view similar to FIG. 1 but showing a third preferred form ofswitching power supply according to the invention;

FIG. 9 is also a view similar to FIG. 1 but showing a fourth preferredform of switching power supply according to the invention;

FIG. 10 is also a view similar to FIG. 1 but showing a fifth preferredform of switching power supply according to the invention;

FIG. 11 is also a view similar to FIG. 1 but showing a sixth preferredform of switching power supply according to the invention;

FIG. 12 is also a view similar to FIG. 1 but showing a seventh preferredform of switching power supply according to the invention;

FIG. 13 is also a view similar to FIG. 1 but showing an eighth preferredform of switching power supply according to the invention;

FIG. 14 is a view similar to FIG. 2 but showing a modified switchcontrol circuit for use in any of the foregoing forms of switching powersupplies in place of the FIG. 2 switch control circuit;

FIG. 15, consisting of (A) through (J), is a series of diagrams showingthe voltage waveforms appearing at various parts of the FIG. 14 switchcontrol circuit;

FIG. 16 is a view similar to FIG. 1 but showing a further preferred formof switching power supply according to the invention;

FIG. 17 is a view similar to FIG. 2 but showing another modified switchcontrol circuit which is included in the FIG. 16 power supply;

FIG. 18 is a schematic electrical diagram, partly in block form, showingin more detail the low-voltage detector circuits included in the FIG. 17embodiment; and

FIG. 19, consisting of (A) through (I), is a series of diagrams showingthe voltage waveforms appearing at various parts of the FIG. 18circuitry.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The switching power supply shown in FIG. 1 by way of a preferableembodiment of the invention has a pair of input terminals 1 and 2 whichare to be connected to a source, not shown, of commercial a.c. voltageV_(ac) with a frequency of, for instance, 50 Hz. A noise filter 3 isconnected to this pair of input terminals 1 and 2. The noise filter 3can be of the conventional make comprising inductors and capacitors forremoval of high-frequency noise from the incoming fixed-frequencyalternating current.

The noise filter 3 is connected to a rectifier circuit 4 having a first41 and a second 42 input, four diodes D₁₁, D₁₂, D₁₃ and D₁₄ in bridgeconnection, and a first 43 and a second 44 output. The pair of rectifierinputs 41 and 42 are connected to the pair of a.c. inputs 1 and 2,respectively, via the noise filter 3. The rectifier circuit 4 makesfull-wave rectification of the incoming a.c. voltage V_(ac) and producesan output voltage V₄ between the pair of outputs 43 and 44.

The output 43 of the rectifier circuit 4 is connected via a currentdetector 9 to a first extremity of a main inductance coil or a maininductor L₁ which is wound on a magnetic core 10. The main inductor L₁is intended for both power factor improvement and for voltage step-up.The second extremity of the main inductor L₁ is connected to anancillary inductance coil or an ancillary inductor L_(a) which is shownincluded in an ancillary soft-switching circuit 7. The ancillaryinductor L_(a) is wound on the same magnetic core 10 as is the maininductor L₁. It is understood that both main inductor L₁ and ancillaryinductor L_(a) have leakage inductance.

A first main switch Q₁ is connected between the second extremity of themain inductor L₁ and the second output 44 of the rectifier circuit 4.Shown as an insulated-gate field-effect transistor, the first mainswitch Q₁ is intended for intermittent voltage application to the maininductor L₁. Connected reversely in parallel with the first main switchQ₁ is a diode D_(q1) which will be hereinafter referred to as the firstparallel diode. In practice, however, a diode built into the first mainswitch Q₁, or the so-called “body diode” thereof, could serve thepurposes of the first parallel diode D_(q1).

A first soft-switching capacitor C_(q1) is also shown connected inparallel with the first main switch Q₁. The provision of this discretesoft-switching capacitor is not an absolute requirement, either; inpractice, its purposes may be served by the parasitic capacitancebetween the drain and source of the first main switch Q₁.

A smoothing capacitor C₁, preferably an electrolytic capacitor, isconnected in parallel with the first main switch Q₁ via a rectifyingdiode D₁. The rectifying diode D₁ is nonconductive during eachconducting period of the first main switch Q₁, and conductive duringpart or whole of each nonconducting period of the first main switch. Thesmoothing capacitor C₁ functions as d.c. power supply for thed.c.-to-d.c. converter circuit yet to be described.

At 5 is shown a transformer having a primary winding N₁, a secondarywinding N₂, and a tertiary winding or a second ancillary inductor L_(b),all wound around a magnetic core 9 and electromagnetically coupledtogether. The three transformer windings N₁, N₂ and L_(b) are polarizedas marked with the dots in FIG. 1. It will be seen from the markingsthat the transformer primary N₁ and secondary N₂ are opposite inpolarity. The transformer primary N₁ has one of its opposite extremitiesconnected directly to one of the opposite polarity terminals of thesmoothing capacitor C₁, and the other extremity connected to the otherterminal of the smoothing capacitor C₁ via a second main switch Q₂; inother words, the smoothing capacitor C₁ is in parallel with the serialconnection of transformer primary N₁ and second main switch Q₂.

Like the first main switch Q₁, the second main switch Q₂ is shown as aninsulated-gate field-effect transistor, having a drain connected to thetransformer primary N., and a source connected to the smoothingcapacitor C₁. This second main switch Q₂ also has a second paralleldiode D_(q2) connected reversely in parallel therewith. This secondparallel diode D_(q2) could also be replaced by an inbuilt diode, orbody diode, of the second main switch Q₂.

The second main switch Q₂ has its own soft-switching capacitor C_(q2)(hereinafter referred to as the second soft-switching capacitor incontradistinction from the first recited soft-switching capacitorC_(q1)) connected in parallel therewith. The second soft-switchingcapacitor C_(q2) would also be unnecessary if the second main switch Q₂had a sufficient amount of parasitic capacitance between its drain andsource. Also, like the first soft-switching capacitor C_(q1), the secondsoft-switching capacitor C_(q2) is less in capacitance than thesmoothing capacitor C₁.

The transformer secondary N₂ has its opposite extremities connectedrespectively to the pair of output terminals 12 and 13 via a rectifyingand smoothing circuit 6. The rectifying and smoothing circuit 6comprises a rectifying diode D₀ and a smoothing capacitor C₀. Thecapacitor C₀ is connected in parallel with the transformer secondary N₂via the diode D₀. Connected between one extremity of the transformersecondary N₂ and the output terminal 12, the diode D₀ is so oriented asto be conductive when the second main switch Q₂ is off, andnonconductive when the second main switch Q₂ is on. A unidirectionaloutput voltage is thus obtained between the pair of output terminals 12and 13 for feeding a load 14 connected thereto.

The present invention particularly features the noted ancillarysoft-switching circuit 7 which comprises an ancillary switch Q₃, thenoted first ancillary inductor L_(a), two reverse-blocking diodes D_(a)and D_(b), and the noted second ancillary inductance coil or secondancillary inductor L_(b). Wound on the same magnetic core 10 as is themain inductor L₁, the first ancillary inductor L_(a) has one extremitythereof connected to the output-side extremity of the main inductor L₁,and the other extremity connected to the ancillary switch Q₃ via thefirst reverse-blocking diode D_(a). As indicated by the dashed line inFIG. 1, an additional inductor L₁₁ may be connected in series with thefirst ancillary inductor L_(a) in cases where the first ancillaryinductor fails to provide sufficient inductance for the desired softswitching of the first main switch Q₁.

Wound around the transformer core 11 as its tertiary winding so as topossess leakage inductance, the second ancillary inductor L_(b) has oneextremity thereof connected to the junction P₂ between transformerprimary N₁ and the drain of the second main switch Q₂. The otherextremity of the second ancillary inductor L_(b) is connected to theancillary switch Q₃ via the second reverse-blocking diode D_(b). Hereagain, as indicated by the dashed line in FIG. 1, another additionalinductor L₁₂ may be connected in series with the second ancillaryinductor L_(b) in cases where this second ancillary inductor fails toprovide sufficient inductance for the soft switching of the second mainswitch Q₂.

The ancillary switch Q₃, shown as an insulated-gate field-effecttransistor, functions for the soft switching of both first and secondmain switches Q₁ and Q₂. Toward this end the ancillary switch Q₃ isconnected in parallel with the first soft-switching capacitor C_(q1) viathe first reverse-blocking diode D_(a) and first ancillary inductorL_(a), and in parallel with the second soft-switching capacitor C_(q2),too, via the second reverse-blocking diode D_(b) and second ancillaryinductor L_(b).

FIG. 1 also shows a switch control circuit 8 for controllably drivingall of the two main switches Q₁ and Q₂ and the ancillary switch Q₃. Theswitch control circuit 18 has inputs connected to the pair of d.c.output terminals 12 and 13 by way of conductors 15 and 16 for detectingthe d.c. output voltage V₀, and outputs connected to the gates of thetwo main switches Q₁ and Q₂ by way of conductors 17 and 18, and to thegate of the ancillary switch Q₃ by way of a conductor. The switchcontrol circuit 8 is connected to the sources of all these switches Q₁,Q₂ and Q₃ as well. Moreover, for power factor improvement, the switchcontrol circuit 8 is connected to the noted current detector 9 by way ofa conductor 20, and to the first output 43 of the rectifier circuit 4 byway of a voltage-detecting conductor 21. One of the opposite polarityterminals of the smoothing capacitor C₁ is also connected to the switchcontrol circuit 8 by way of a conductor 22 for holding constant thevoltage V_(c1) across the smoothing capacitor. The switch controlcircuit 8 delivers a first main switch control signal V_(g1) over theconductor 17 to the first main switch Q₁ for driving the same, a secondmain switch control signal V_(g2) over the conductor 18 to the secondmain switch Q₂ for driving same, and an ancillary switch control signalV_(g3) over the conductor 19 to the ancillary switch Q₃ for driving thesame.

As illustrated in detail in FIG. 2, the switch control circuit 8 broadlycomprises a first main switch control circuit 61 for determination ofthe conducting periods of the first main switch Q₁, a second main switchcontrol circuit 62 for determination of the conducting periods of thesecond main switch Q₂, a periodic wave generator 29, two timers 34 and37, and two AND gates 35 and 36. The first main switch control circuit61 controls the conducting periods of the first main switch Q₁ so as tohold the voltage across the smoothing capacitor C₁ at a desired valueand to cause the input current of the rectifier circuit 4 to approximatea sinusoidal wave in waveform. The second main switch control circuit 62controls the conducting periods of the second main switch Q₂ so as tohold the output voltage of the rectifying and smoothing circuit 6 at adesired value. The periodic wave generator 29 might be considered a partof both first and second main switch control circuits 61 and 62.

The first main switch control circuit 61 includes a rectifier outputvoltage detector circuit 23 as a rectifier terminal voltage detectorconnected by way the conductor 21 to the first output 43, FIG. 1, of therectifier circuit 4. The rectifier output voltage detector circuit 23takes fier circuit 4. The rectifier output voltage detector circuit 23takes the form of a serial connection of two resistors R₁ and R₂ fordividing the rectifier output voltage V₄, the latter being the result offull-wave rectification of the incoming a.c. voltage of sinusoidalwaveform. The output from the rectifier output voltage detector circuit23 is designated V₄′.

Also included in the first main switch control circuit 61 is a capacitorvoltage detector circuit 24 which is connected to the smoothingcapacitor C₁, FIG. 1, by way of the conductor 22. Dividing the capacitorvoltage V_(c1) by a serial connection of two resistors R₃ and R₄, thecapacitor voltage detector circuit 24 puts out a voltage V_(c1)′ fordelivery to a subtracter 26. This subtracter puts out a differencebetween the capacitor voltage detector output voltage V_(c1)′ and areference voltage V_(r1) from its source 26 _(a). The subtracter outputis directed into a multiplier 27.

The multiplier 27 has another input connected to the rectifier outputvoltage detector circuit 23. The output V₂₇ from the multiplier 27 istherefore the product of the output V₄′ from the rectifier outputvoltage detector circuit 23 and the output from the subtracter 26. Themultiplier output V₂₇ has a waveform like that resulting from afull-wave rectification of a sinusoidal wave. The multiplier outputvoltage V₂₇ has its amplitude so adjusted as to keep constant thesmoothing capacitor voltage V_(c1) by the output from the subtracter 26.

A second subtracter 28 has one input connected to the multiplier 27, andanother input connected to the current detector 9, FIG. 1, by way of theconductor 20. The current detector 9 provides a voltage V₉ in proportionwith the magnitude of the current I₄ issuing from the first output 43 ofthe rectifier circuit 4. The output from the second subtracter 28 istherefore the difference V₂₈ between the multiplier output voltage V₂₇and the current detector output voltage V₉. This second subtracteroutput V₂₈ is directed into a comparator 30, the final-stage componentof the first main switch control circuit 61.

The periodic wave generator 29 bears the generic name encompassinggenerators of any suitable types of periodic voltage waveforms. It takesthe form of a sawtooth generator in this particular embodiment, puttingout on its output 29 _(a) a sawtooth voltage V_(t) with a frequency of,say, 20 kHz, which is much higher than that of the a.c. input voltage tobe applied between the pair of input terminals 1 and 2. This sawtoothvoltage frequency determines the switching frequency of the two mainswitches Q₁ and Q₂ and the ancillary switch Q₃. It is understood thatthe sawtooth generator 29 has a clock, not shown, built into it forsynchronization of the sawtooth voltage. This clock is utilized for theadditional purposes of synchronously triggering the timers 34 and 37 inthis embodiment, so that the sawtooth generator 29 is furnished withanother output 29 _(b) for delivering the clock pulses V_(osc) to thetimers.

Although but one sawtooth generator 29 is shown provided to help producethe three control signals V_(g1), V_(g2) and V_(g3) for the two mainswitches Q₁ and Q₂ and one ancillary switch Q₃, two or three sawtooth orother periodic wave generators could be employed for the same purposes.As an additional possible modification of this illustrated embodiment,the timers 34 and 37 could be triggered by pulses fabricated from thesawtooth voltage V_(t), instead of by the clock pulses V_(osc).

The output 29 _(a) of the sawtooth generator 29 is connected to oneinput of the comparator 30 of the first main switch control circuit 61for delivery of the sawtooth voltage V_(t) thereto. The other input ofthe comparator 30 is connected as aforesaid to the second subtracter 28for inputting its output voltage V₂₈.

At (A) in FIG. 3 is shown the series of clock pulses V_(osc) which isgenerated by the unshown clock built into the sawtooth generator 29 andwith which the sawtooth voltage V_(t) is synchronized. The same figureindicates at (B) both the sawtooth voltage V_(t) and the secondsubtracter output voltage V₂₈. Comparing these two inputs, thecomparator 30 will produce the rectangular wave output V₃₀ seen at (C)in FIG. 3. This comparator output V₃₀ tentatively predefines theconducting periods of the first main switch Q₁. The actual conductingperiods of the first main switch Q₁ are yet to be redefined in a mannerthat will become apparent as the description progresses.

The second main switch control circuit 62 includes an output voltagedetector circuit 25 having two voltage-dividing resistors R₅ and R₆interconnected in series between the pair of input conductors 15 and 16and hence between the pair of outputs 12 and 13, FIG. 1, of this powersupply. Thus the output voltage detector circuit 25 provides a voltageV₀′ in proportion with the power supply output voltage V₀. The outputvoltage detector circuit 25 is connected to one input of a subtracter32, the other input of which is connected to a source 31 of referencevoltage V_(r2). The resulting output from the subtracter 32 is thedifference V₃₂ between the output voltage detector output V₀′ and thereference voltage V_(r2).

A comparator 33, the final-stage component of the second main switchcontrol circuit 62, has one input connected to the output 29 a of thesawtooth generator 29, and another input connected to the subtracter 32.As indicated at (D) in FIG. 3, the comparator 33 will compare thesawtooth voltage V_(t) and the subtracter output voltage V₃₂ and producethe rectangular wave output V₃₃ seen at (E) in FIG. 3. This comparatoroutput V₃₃ tentatively predefines the conducting periods of the secondmain switch Q₂, FIG. 1. The actual conducting periods of the second mainswitch Q₂ are yet to be redefined.

The actual conducting periods of the two main switches Q₁ and Q₂ areunder limitations to be imposed by the first timer 34, which has itsinput connected to the second output 29 _(b) of the sawtooth generator29. Triggered by each clock pulse V_(osc), FIG. 3(A), or by each rise ofthe sawtooth wave, FIG. 3(B), as at t₀, the first timer 34 will put outa “negative” pulse of first predetermined duration T₁, FIG. 3(F), asfrom t₀ to t₁.

The comparator 30 of the first main switch control circuit 61 and thefirst timer 34 are both connected to the AND gate 35 as a first logiccircuit. The output from the AND gate 35 is the first main switchcontrol signal V_(g1), FIG. 3(G), which represents the logical productof the comparator output voltage V₃₀, FIG. 3(C), and the first timeroutput voltage V₃₄, FIG. 3(F). The first main switch control signalV_(g1) will be delivered over the conductor 17 to the first main switchQ₁, FIG. 1, causing conduction therethrough as from t₁ to t₃ in FIG. 3.

The other AND gate 36 as a second logic circuit has its inputs connectedto the first timer 34 and to the comparator 33 of the second main switchcontrol circuit 62. The output from this AND gate 36 is the second mainswitch control signal V_(g2), FIG. 3(H), which represents the logicalproduct of the comparator output voltage V₃₃, FIG. 3(E), and the firsttimer output voltage V₃₄, FIG. 3(F). The second main switch controlsignal V_(g2) will be delivered over the conductor 18 to the second mainswitch Q₂, FIG. 1, causing conduction therethrough as from t₁ to t₄ inFIG. 3.

Connected to the clock pulse output 29 _(b) of the sawtooth generator29, the second timer 37 puts out the ancillary switch control signalV_(g3), FIG. 3(I), for delivery to the ancillary switch Q₃ over theconductor 19. The ancillary switch control signal V_(g3) includes pulsesof second predetermined duration T₂, lasting as from t₀ to t₂ in FIG. 3,which rise in synchronism with the rises of the sawtooth voltage V_(t).The duration T₂ of the ancillary switch control pulses V_(g3) is longerthan the duration T₁ of each “negative” output pulse V₃₄ of the firsttimer 34.

As is clear from a comparison of the three switch control signalsV_(g1), V_(g2) and V_(g3) at (G), (H) and (I) in FIG. 3, the ancillaryswitch Q₃ is turned on at t₀ which is earlier by T₁ than t₁ when the twomain switches Q₁ and Q₂ are both turned on. Thus is accomplished thesoft turn-on of the main switches Q₁ and Q₂. The period T₁ should lastfrom t₀, when the ancillary switch Q₃ is turned on, to the moment whenthe main switch voltages V_(q1) and V_(q2) becomes substantially zero orless than the voltage during the nonconducting periods of the mainswitches Q₁ and Q₂. The moment t₂ when the ancillary switch controlsignal V_(g3) goes low, causing nonconduction through the ancillaryswitch Q₃, should be not later than t₃ when either of the two mainswitches Q₁ and Q₂ terminates conduction earlier than the other.

For an easier understanding of the basic operation of the FIG. 1 powersupply, such operation will now be explained on the assumption that theancillary soft-switching circuit 7 were nonfunctional. FIG. 4 shows thevoltage and current waveforms that would appear at various parts of theFIG. 1 circuitry should the ancillary switch Q₃ of the ancillarysoft-switching circuit 7 be held off.

The rectifier output voltage V₄, the result of full-wave rectificationof the incoming a.c. voltage V_(ac), FIG. 4(D), will be intermittentlyapplied to the main inductor L₁ if the first main switch Q₁ is turned onand off by the first main switch control signal V_(g1), FIG. 4(A).During each conducting period T_(on) of the first main switch Q₁, asfrom t₁ to t₂ in FIG. 4, the rectifier output current I₄ will flow alongthe path comprising the first output 43 of the rectifier circuit 4, themain inductor L₁, the first main switch Q₁, and the second output 44 ofthe rectifier circuit 4. As indicated at (B) in FIG. 4, the current I₄will increase in magnitude with time owing to the inductance of the maininductor L₁ during each conducting period T_(on) of the first mainswitch Q₁. Energy will be stored on the inductor during each suchperiod.

At t₂ in FIG. 4, when the first main switch Q₁ goes off, the inductor L₁will start releasing the stored energy, causing conduction through thediode D₁ as the sum of the rectifier output voltage V₄ and the voltageacross the main inductor L₁ grows higher than the voltage V_(c1) acrossthe smoothing capacitor C₁. Current will then flow along the pathcomprising the first rectifier output 43, main inductor L₁, diode D₁,smoothing capacitor C₁, and second rectifier output 44, thereby chargingthe smoothing capacitor. The rectifier output current 14 will decreasein magnitude during each nonconducting period T_(off) of the first mainswitch Q₁. Although the rectifier output current I₄ is shown in FIG. 4as flowing until t₄ when the next conducting period T_(on) starts, theinductance value of the inductor L₁ may be so determined that thecurrent I₄ may drop to zero as at t₃ which precedes t₄, as indicated bythe dashed line in FIG. 4.

The rectifier output current I₄ during the conducting periods T_(on) ofthe first main switch Q₂ change in peak value in proportion with theinstantaneous value of the rectifier output voltage V₄. Consequently, aswill be noted from (C) and (D) in FIG. 4, the a.c. input I_(ac) willapproximate the input a.c. voltage V_(ac) in phase and becomesinusoidal, or approximately so. Improvement in power factor will thenbe accomplished by turning the first main switch Q₁ on and off at arepetition frequency higher than that of the input a.c. voltage.Moreover, thanks to voltage boosting by the main inductor L₁, thesmoothing capacitor C₁ will be charged to a voltage higher than therectifier output voltage V₄.

The conducting periods of the first main switch Q₁ will become shorterif the voltage V_(c1) across the smoothing capacitor C₁ becomes higherthan normal. The voltage V_(c1) will return to normal as correspondinglyless energy is stored on the main inductor L₁. On the other hand, if thevoltage V_(c1) becomes less than normal, the conducting periods of thefirst main switch Q₁ will become longer. Correspondingly more energywill be stored on the main inductor L₁ until the voltage V_(c1) returnsto normal.

The following is a discussion of d.c.-to-d.c. conversion by the actionof the second main switch Q₂ in the absence of the ancillarysoft-switching circuit 7. The voltage V_(c1) across the smoothingcapacitor C₁ will be impressed to the transformer primary N₁ uponconduction of the second main switch Q₂. The voltage induced then acrossthe transformer secondary N₂ will be oriented to reverse-bias the diodeD₀, holding the same nonconductive. The energy thus stored on thetransformer 5 will be released upon subsequent nonconduction of thesecond main switch Q₂. The diode D₀ will then conduct, permitting thecapacitor C₀ to be charged. Here again, if the power supply outputvoltage V₀ across the capacitor C₀ becomes higher than normal, theconducting periods of the second main switch Q₂ will become shorter. Theoutput voltage V₀ will return to normal as correspondingly less energyis stored on the transformer 5. The conducting periods of the secondmain switch Q₂ will become longer when the output voltage V₀ becomesless than normal. Correspondingly more energy will then be stored on thetransformer 5, causing the output voltage V₀ to return to normal.

Reference may be had to the waveform diagram of FIG. 5 for the followingexplanation of soft switching by the two main switches Q₁ and Q₂. Themain switches Q₁ and Q₂ and the ancillary switch Q₃ are all off beforet₁, as well as from t₁₃ to t₁₄, in FIG. 5, as indicated at (A), (B) and(C) in this figure. It has been stated that the smoothing capacitor C₁will be charged by energy release from the main inductor L₁ during thenonconducting period of the first main switch Q₁. The current I_(d1)will therefore flow through the diode D₁ as at (K) in FIG. 5. Since thesecond main switch Q₂ is also off, the current I_(d0) will flow due toenergy release from the transformer 5, along the path comprising thetransformer secondary N₂, diode D₀, and capacitor C₀, as indicated at(H) in FIG. 5. The load 14 will be fed from the capacitor C₀.

The ancillary switch control signal V_(g3) is shown to go high at ti, asat (C) in FIG. 5, causing conduction through the ancillary switch Q₃.Thereupon the voltage across the ancillary switch Q₃ will becomepractically zero as at (H) in FIG. 5. As a result, during the ensuingt₁-t₂ period, the current I_(da) of FIG. 5(K) will flow along the pathcomprising the first rectifier output 43, main inductor L₁, firstancillary inductor L_(a), first reverse-blocking diode D_(a), ancillaryswitch Q₃, and second rectifier output 44. The current I_(db) of FIG.5(L) will also flow during the same ti-t₂ period along the pathcomprising the smoothing capacitor C₁, transformer primary N₁, secondancillary inductor L_(b), second reverse-blocking diode D_(b), andancillary switch Q₃. At (I) in FIG. 5 is shown the current I_(q3)through the ancillary switch Q₃, which current is the sum of the FIG.5(K) current I_(da) and the FIG. 5(L) current I_(db). The currentsI_(da) and I_(db) will gain in magnitude because of the presence ofinductances in their flow paths. A zero-current turn-on of the ancillaryswitch Q₃ thus accomplished, causing no power loss.

Upon conduction of the ancillary switch Q₃ at t₁ as above, the serialcircuit of the first ancillary inductor L_(a), first reverse-blockingdiode D_(a), and ancillary switch Q₃ will be connected in parallel withthe serial circuit of the diode D₁ and smoothing capacitor C₁. Thevoltage V_(c1) across the smoothing capacitor C₁ will be impressed tothe junction P₁ between main inductor L₁ and first ancillary inductorL_(a) via the diode D₁ as long as this diode is conductive. The firstsoft-switching capacitor C_(q1) will therefore be clamped by the voltageV_(c1) across the smoothing capacitor C₁ while the diode D₁ isconductive, so that the first soft-switching capacitor C_(q1) will notstart discharging immediately upon conduction of the ancillary switch Q₃at t₁.

After t₁, when the ancillary switch Q₃ and rectifying diode D₁ are bothconductive, the voltage V_(c1) across the smoothing capacitor C₁ will beimpressed via the diode D₁ to the serial circuit of the first ancillaryinductor L_(a), first reverse-blocking diode D_(a) and ancillary switchQ₃. The current I_(da) flowing through this serial circuit willgradually increase in magnitude as at (K) in FIG. 5. Since the serialcircuit of the first ancillary inductor L_(a), first reverse-blockingdiode D_(a) and ancillary switch Q₃ is connected as aforesaid inparallel with the serial circuit of the diode D₁ and smoothing capacitorC₁ after t₁, when both rectifying diode D₁ and ancillary switch Q₃ areconductive as above, the current supplied by the main inductor L₁ willbe divided between the two serial circuits. As indicated at (M) in FIG.5, therefore, the current flowing through the rectifying diode D₁ willdrop in magnitude more rapidly than before t₁.

The current supplied by the main inductor L₁ will decrease in magnitudeupon voltage application to the first ancillary inductor L_(a) at t₁ inFIG. 5 because the main inductor L₁ and first ancillary inductor L_(a)are electromagnetically coupled together. The result will be arelatively rapid drop in the magnitude of the current I_(d1) through therectifying diode D₁, to zero at t₄ in FIG. 5.

At (L) in FIG. 5 is shown the current I_(db) which flows along the pathcomprising the transformer primary N₁ and second ancillary inductorL_(b) from t₁ to t₂. As a result, as indicated at (J) in FIG. 5, agradual drop will occur, finally to zero at t₂, in the magnitude of thecurrent I_(d0) which is supplied to the diode D₀ from the transformersecondary N₂ electromagnetically coupled to the transformer primary N₁and second ancillary inductor L_(b).

At t₂, when the diode D₀ of the rectifying and smoothing circuit 6becomes nonconductive, the transformer secondary N₂ will be unclampedfrom the voltage V₀ across the capacitor C₀. As the secondsoft-switching capacitor C_(q2) is thus enabled to discharge, aresonance circuit will be completed which is constituted of thecapacitance of the second soft-switching capacitor C_(q2) and theinductance of the second ancillary inductor L_(b). The discharge currentI_(cq2) of the second soft-switching capacitor C_(q2) will flow alongthe path comprising the capacitor C_(q2), second ancillary inductorL_(b), second reverse-blocking diode D_(b), and ancillary switch Q₃, asindicated at (O) in FIG. 5. As a result, as shown at (F) in FIG. 5, thevoltage V_(q2) across the second soft-switching capacitor C_(q2) andsecond main switch Q₂ will diminish to zero at t₃.

During this t₂-t₃ period, as during the previous t₁-t₂ period, thecurrent I_(da) will flow along the path comprising the first rectifieroutput 43, main inductor L₁, first ancillary inductor L_(a), firstreverse-blocking diode D_(a), ancillary switch Q₃, and second rectifieroutput 44. The current I_(db) will flow along the path comprising thesmoothing capacitor C₁, transformer primary N₁, second ancillaryinductor L_(b), second reverse-blocking diode D_(b), and ancillaryswitch Q₃. The current I_(d1) through the diode D₁ will also flow.

At t₃, when the second soft-switching capacitor C_(q2) completes itsdischarge, the current I_(q2) will start flowing as at (G) in FIG. 5along the path comprising the second ancillary inductor L_(b), secondreverse-blocking diode D_(b), ancillary switch Q₃, and second paralleldiode D_(q2), due to energy release from the second ancillary inductorL_(b). The current I_(q2) is shown at (G) in FIG. 5 as the sum of thecurrent flowing through the drain and source of the second main switchQ₂ and the current through the second parallel diode D_(q2). However,for ease of description, this current I_(q2) will be hereinafterreferred to as the current through the second main switch Q₂.

The drain-source voltage V_(q2) of the second main switch Q₂ will remainzero, or very low, as long as the second parallel diode D_(q2) isconductive. The voltage V_(c1) across the smoothing capacitor C, willtherefore be impressed to the transformer primary N₁.Electromagnetically coupled to the transformer primary N₁, the secondancillary inductor L_(b) will also have impressed thereto a voltageoriented to decrease the current flowing therethrough. Thus, asindicated at (L) in FIG. 5, the current I_(db) through the secondreverse-blocking diode D_(b) will start diminishing at t₃. The currentI_(d1) through the diode D₁ and the current I_(da) through the firstreverse-blocking diode D_(a) will continue flowing from t₃ to t₄, asfrom t₂ to t₃.

The diode D₁ will become nonconductive at t₄ when the current I_(d1)flowing through the diode D₁ into the smoothing capacitor C₁ becomeszero. Thereupon, unclamped from the smoothing capacitor C₁, the firstsoft-switching capacitor C_(q1) will start discharging. The currentI_(cq1) through the first soft-switching capacitor C_(q1) will flow asat (N) in FIG. 5. The current I_(cq1) due to the discharge of the firstsoft-switching capacitor C_(q1) will flow by the resonant circuitcontaining the capacitance of the first soft-switching capacitanceC_(q1) and the inductance of the first ancillary inductor L_(a); thatis, during the t₄-t₅ period, the discharge current J_(cq1) will flowalong the path sequentially comprising the first soft-switchingcapacitor C_(q1), first ancillary inductor L_(a), first reverse-blockingdiode D_(a), and ancillary switch Q₃.

As shown at (D) in FIG. 5, the voltage V_(q1) across the first mainswitch Q₁ will start diminishing at t₄ with the progress of thedischarge by the first soft-switching capacitor C_(q1) until it becomeszero at t₅. In the course of such diminution of the first main switchvoltage V_(q1), the potential at the junction P₁ between main inductorL₁ and first ancillary inductor L_(a) will equal the potential at thefirst output 43 of the rectifier circuit 4 approximately in the middleof the t₄-t₅ period, as indicated at t₄′ in FIG. 5. The potential at thejunction P₁ will continue dropping thereafter below that at the firstrectifier output 43.

Thus the voltage across the main inductor L₁ will be reversed inorientation at t₄′, and so will be the voltage across the firstancillary inductor L_(a) because these two inductors areelectromagnetically coupled together. As a result, as will be seen from(K) in FIG. 5, the current I_(da) through the first ancillary inductorL_(a) will start diminishing at t₄′.

At (A) and (B) in FIG. 5 are shown both first and second main switchcontrol signals V_(g1) and V_(g2) as going high at t₅ to turn both mainswitches Q₁ and Q₂ on at that moment. Since the voltage V_(q1) acrossthe first main switch Q₁ drops to zero at t₅, as at (D) in FIG. 5, thefirst main switch Q_(q) is turned on at zero voltage in order to savepower. In practice, however, the first main switch Q₁ may be turned onat any moment from t₅ to t₆, when the first main switch voltage V_(q1)remains zero. Speaking more broadly, the first main switch Q₁ may beturned on at any moment after t₄, when the voltage V_(q1) across thesame is not zero but less than that at t₄. For, even in this case, powerloss at the turn-on of the first main switch Q₁ will be reduced to anextent to which the first main switch voltage V_(q1) has dropped aftert₄.

The second main switch Q₂ is turned on at the same moment as is thefirst main switch Q₁ for the simplicity of the switch control circuit 8,FIG. 2. The voltage V_(q2) across the second main switch Q₂ has beenzero since t₃, as at (F) in FIG. 5, so that the second main switch couldbe turned on at any moment since then. The current through the secondparallel diode D_(q2), connected in parallel with the second main switchQ₂, flows from t₃ to t₆ in this embodiment, during which period thevoltage V_(q2) across the second main switch is zero or very nearly so.Broadly, therefore, the second main switch Q₂ could be turned on at anymoment from t₃ to t₆.

From t₅ to t₆, when the first main switch Q₁ is conductive, current willflow along the path comprising the first rectifier output 43, firstinductor L₁, first main switch Q₁, and second rectifier output 44. Atthe same time the current I_(da), FIG. 5(K), will also flow along thepath comprising the first ancillary inductor L_(a), firstreverse-blocking diode D_(a), ancillary switch Q₃, and first paralleldiode D_(q1).

At t₆, when the negative-going current through the first parallel diodeD_(q1) becomes zero as at (E) in FIG. 5, the current I_(q1) will startflowing along the path comprising the first rectifier output 43, maininductor L₁, first main switch Q₁ and second rectifier output 44. Thecurrent I_(q1) will increase in magnitude with time. The capacitor C₁will not be charged then because the rectifying diode D₁ isnonconductive when the first main switch Q₁ is conductive. Theliberation of the energy stored the first ancillary inductor L_(a) isnot yet complete at t₆ in this particular embodiment. The currentI_(da), FIG. 5(K), will continue to flow until t₈ for the completerelease of that energy along the path comprising the first ancillaryinductor L_(a), first reverse-blocking diode D_(a), ancillary switch Q₃,and first parallel diode D_(q1).

After t₆, when the negative-going current through the second main switchQ₂ becomes zero, the current I_(q2) will flow as at (G) in FIG. 5 alongthe path comprising the smoothing capacitor C₁, transformer primary N₁,and second main switch Q₂. Although the currents I_(q1) and I_(q2)through the two main switches Q_(q) and Q₂ are shown at (E) and (G) inFIG. 5 as both going positive at t₆, they could do so at differentmoments. Generally, the current I_(q2) will become zero earlier thanI_(q1).

The second ancillary inductor L_(b) completes the release of its storedenergy at t₇, rather than at t₆, in this particular embodiment. Theresidual energy will be released along the path comprising the secondancillary inductor L_(b), second reverse-blocking diode D_(b), ancillaryswitch Q₃, smoothing capacitor C₁, and transformer primary N₁.

The current I_(db) through the second reverse-blocking diode D_(b) isshown at (L) in FIG. 5 as becoming zero at t₇. The current I_(da)through the first reverse-blocking diode D_(a) is shown at (K) in FIG. 5as becoming zero at t₈. During this t₇-t₈ period, only the currentI_(da) through the first reverse-blocking diode D_(a) will flow throughthe ancillary switch Q₃.

The ancillary switches Q₃ is shown turned off at t₉ when the ancillaryswitch control signal V_(g3) goes low as at (C) in FIG. 5. The ancillaryswitch Q₃ will then be turned off at zero current because the currentthrough the ancillary switch has been zero since t₈. Speaking morebroadly, the ancillary switch Q₃ may be turned off at any moment fromt₈, when the current I_(q3) therethrough becomes zero, to t₁₀ when thefirst main switch Q₁ turns on. The first main switch Q₁ is shown turnedoff earlier than the second Q₂ in FIG. 5. If, instead, the second mainswitch Q₂ is to be turned on earlier than the first Q₁, the ancillaryswitch Q₃ should be turned off earlier than the second main switch Q₂ isturned on.

Both main switches Q₁ and Q₂ are conductive, and the ancillary switch Q₃nonconductive, from t₉ to t₁₀. Energy will therefore be stored on themain inductor L₁ by virtue of the current I_(q1) through the first mainswitch Q₁, and on the transformer 5 by virtue of the current I_(q2)through the second main switch Q₂.

At t₁₀, when the first main switch Q₁ is turned off as at (A) in FIG. 5,the current I_(q1) through the first main switch will drop to zero as at(E) in the same figure. The current I_(cq1), FIG. 5(N), will flowinstead into the first soft-switching capacitor C_(q1), charging thesame, and the voltage V_(q1) across this capacitor C_(q1) and first mainswitch Q₁ will build up with a gradient as at (D) in FIG. 5. For thisreason, even if the current I_(q1) through the first main switch Q₁decays with some delay because of the known storage action, less powerloss will occur at the first main switch. The first main switch Q₁ willbe turned off substantially at zero voltage.

The rectifying diode D₁ will conduct at t₁₁ when the voltage V_(q1)across the first main switch Q₁ grows higher than the voltage V_(c1)across the smoothing capacitor C₁. The current I_(d1) will start flowingas at (M) in FIG. 5, and the smoothing capacitor C₁ will begin to becharged.

The current I_(q2) through the second main switch Q₂ will drop to zeroat t₁₂, as at (G) in FIG. 15, when the second main switch is turned off.The voltage V_(q2) across the second soft-switching capacitor C_(q2) andsecond main switch Q₂ will then develop with a gradient as at (F) inFIG. 5. Therefore, even if the current I_(q2) decays belatedly by thestorage action of the second main switch Q₂, less power loss will occurat this second main switch. In short the second main switch Q₂ will beturned off substantially at zero voltage.

What occurred immediately before t₁ in FIG. 5 will repeat itself fromt₁₃ to t₁₄. The smoothing capacitor C₁ will be charged as the maininductor L₁ releases the energy that has been stored thereon. Also, asthe energy that has been stored on the transformer 5 is released, thecapacitor C₀ of the rectifying and smoothing circuit 6 will be chargedfrom the transformer secondary N₂ via the diode D₀. One cycle ofoperation has come to an end at t₁₄. The same cycle will repeat itselfafter t₁₄.

The advantages gained by this FIGS. 1-5 embodiment may be recapitulatedas follows:

1. Both main switches Q₁ and Q₂ share the single ancillary switch Q₃ forsoft switching. The power supply is therefore is significantly simplerin construction than if two ancillary switches were employed for therespective main switches in combination with associated control meansfor the ancillary switches. The soft switching of the main switches isessential for curtailment of power losses at these switches and of noiseproduction.

2. The two main switches Q₁ and Q₂ are both driven at the samerepetition frequency, thereby keeping them from unstable operation andnoise production that would result from mutual frequency interference iftwo different frequencies were employed for driving them.

3. The control signals V_(g1) and V_(g2) for the two main switches Q₁and Q₂ are capable of fabrication by relatively simple circuit meansshown in FIG. 2, as the main switches are turned on simultaneously.

4. The first ancillary inductor L_(a) with leakage inductance is woundon the same magnetic core as is the main inductor L₁. The resonantinductor is therefore manufacturable more compactly and inexpensivelythan if a discrete inductor were employed to provide the inductance forinductance-capacitance resonance.

5. The first ancillary inductor L_(a) is electromagnetically coupled tothe main inductor L₁. As a result, upon voltage application to the firstancillary inductor L_(a) while the ancillary switch Q₃ is conductive,there is induced across the main inductor L₁ the voltage that isoriented to reduce the current flowing therethrough. The result is arapid drop, starting from t₁, in the magnitude of the current I_(d1)through the rectifying diode D₁, as indicated at (M) in FIG. 5.

6. Formed as a part of the transformer so as to possess leakageinductance, the second ancillary inductor L_(b) constitutes a resonantcircuit in combination with the second soft-switching capacitor C_(q2).The inductor for resonance is thus manufacturable more compactly andinexpensively than as a discrete unit.

7. The second ancillary inductor L_(b) is electromagnetically coupled tothe transformer primary N₁ and secondary N₂. Therefore, by turning onthe ancillary switch Q₃ at t₁ in FIG. 5 for current flow through thesecond ancillary inductor L_(b), the current I_(d0) through the diode D₀of the rectifying and smoothing circuit 6 can be caused to drop rapidlyin magnitude from t₁.

Embodiment of FIGS. 6 and 7

The FIG. 6 power supply differs from that of FIG. 1 in incorporating amodified rectifying and smoothing circuit 6 _(a) in substitution for itsFIG. 1 counterpart 6 and having a transformer secondary N_(2a) which isopposite in polarity to its FIG. 1 counterpart N₂. The circuitconfiguration from the pair of input terminals 1 and 2 to the primarywinding N₁ of the transformer 5 of the FIG. 6 device is akin to that ofFIG. 1. The d.c.-to-d.c. converter circuit including the second mainswitch Q₂ in this alternate embodiment is what is known as the forwardd.c.-to-d.c. converter, causing conduction through the diode D₀ by thevoltage developing across the transformer secondary N_(2a) when thesecond main switch Q₂ is conductive.

The modified rectifying and smoothing circuit 6 _(a) comprises asmoothing inductor L₀ and a smoothing diode D₀₁ in addition to the diodeD₀ and the smoothing capacitor C₀. The inductor L₀ is connected betweendiode D₀ and capacitor C₀. The smoothing diode D₀₁ is connected inparallel with the inductor L₀ via the capacitor C₀.

In the operation of the FIG. 6 embodiment the voltage across thesmoothing capacitor C₁ will be impressed to the transformer primary N₁during the conducting periods of the second main switch Q₂. The voltagedeveloping across the transformer secondary N_(2a) will cause conductionthrough the diode D₀ thereby permitting the smoothing capacitor C₀ to becharged. The diode D₀ will be nonconductive when the second main switchQ₂ is off.

The ancillary soft-switching circuit 7 being of the same construction asits FIG. 1 counterpart, it will be seen that the soft switching of thetwo main switches Q₁ and Q₂ is accomplished just as previously explainedin conjunction with the FIG. 1 embodiment. FIG. 7 is a waveform diagramsimilar to FIG. 5, showing the waveforms of the voltage and currentsignals appearing at various parts of the FIG. 6 circuitry, whichsignals are per se the same as those given in FIG. 5. In FIG. 7,however, the ancillary switch control signal V_(g3) for the ancillaryswitch Q₃ is shown at (C) as going high at t₂, instead of at t₁ as inFIG. 5. As the voltage V_(q3) across the ancillary switch Q₃ drops tozero at t₂ as at (H) in FIG. 7, the current I_(q3) through the ancillaryswitch Q₃ will start flowing at t₂ as at (I) in FIG. 7. The currentI_(da) through the first reverse-blocking diode D_(a) and the currentI_(db) through the second reverse-blocking diode D_(b) will both alsostart flowing at t₂, as at (K) and (L) in FIG. 7. The d.c.-to-d.c.converter circuit including the second main switch Q₂ being of the“forward” design, the current I_(d0) through the diode D₀ of themodified rectifying and smoothing circuit 6 _(a) will flow from t₅ tot₁₂ as at (J) in FIG. 7.

Upon conduction of the ancillary switch Q₃, current will immediatelystart flowing along the path comprising the second soft-switchingcapacitor C_(q2), second ancillary inductor L_(b), secondreverse-blocking diode D_(b), and ancillary switch Q₃. The secondsoft-switching capacitor C_(q2) will thus start discharging. Thesubsequent soft-switching of the two main switches Q₁ and Q₂ willproceed just as previously discussed with reference to FIG. 5. Thus theFIG. 6 embodiment gains the same advantages as that of FIG. 1.

Embodiment of FIG. 8

The switching power supply shown in FIG. 8 is similar to that of FIG. 1except for a modified ancillary soft-switching circuit 7 _(a). Thismodified circuit 7 _(a) has the main inductor L₁ and the first ancillaryinductor L_(a) interconnected in parallel, instead of in series as inFIG. 1. However, as in the FIG. 1 embodiment, the first ancillaryinductor L_(a) is wound on the same core 10 as the main inductor L₁ soas to possess leakage inductance, and both inductors areelectromagnetically coupled together. Each of the inductors L₁ and L_(a)has one extremity thereof connected to the first output 43 of therectifier circuit 4.

The basic operation of the FIG. 8 power supply, as well as that of theancillary soft-switching circuit 7, is as set forth above in connectionwith the FIG. 1 embodiment. The FIG. 5 voltage and current waveformsappearing at various parts of the FIG. 1 circuitry also appear at thesame parts of that of FIG. 8. The operation of the FIG. 8 embodimentwill therefore be explained with reference to FIG. 5. The ancillaryswitch Q₃ being conductive during the t₁-t₂ period in FIG. 5, thecurrent I_(da) will flow as at (K) in this figure along the pathcomprising the first rectifier output 43, first ancillary inductorL_(a), first reverse-blocking diode D_(a), ancillary switch Q₃, andsecond rectifier output 44. The current I_(db) will also flow as at (L)in FIG. 5 along the path comprising the smoothing capacitor C₁,transformer primary N₁, second ancillary inductor L_(b), secondreverse-blocking diode D_(b), and ancillary switch Q₃.

The main inductor L₁ continues its energy liberation during this t₁-t₂period, as before t₁. By virtue of this energy liberation the currentI_(d1) will flow as at (M) in FIG. 5 to the smoothing capacitor C₁ viathe rectifying diode D₁, and the current I_(da) will also flow as at (K)in FIG. 5 through the first ancillary inductor L_(a) electromagneticallycoupled to the main inductor L₁. As a result, in this FIG. 8 embodimenttoo, the current I_(d1) through the rectifying diode D₁ will diminish asat (M) in FIG. 5 with a steeper gradient than before upon conduction ofthe ancillary switch Q₃.

The voltage V_(q2) across the second main switch Q₂ will drop to zero byresonance during the t₂-t₃ period. The first soft-switching capacitorC_(q1) will be set free from clamping by the voltage V_(c1) across thesmoothing capacitor C₁ at t₄ when the rectifying diode D₁ becomesnonconductive. As a consequence, during the ensuing t₄-t₅ period,resonance current will flow along the path comprising the firstsoft-switching capacitor C_(q1), main inductor L₁, first ancillaryinductor L_(a), first reverse-blocking diode D_(a), and ancillary switchQ₃. As the energy is thus transferred from first soft-switchingcapacitor C_(q1) to first ancillary inductor L_(a), the voltage V_(q1)across the first soft-switching capacitor C_(q1) and first main switchQ₁ will drop to zero at t₅. A zero-voltage switching of both mainswitches Q₁ and Q₂ will therefore be achieved by turning these switcheson at t₅ or, more broadly, from t₅ to t₆.

Embodiment of FIG. 9

The FIG. 9 embodiment differs from that of FIG. 8 in having a modifiedrectifying and smoothing circuit 6 _(a) in place of its FIG. 8counterpart 6, and in having a transformer secondary N_(2a) which isopposite in polarity from its FIG. 8 counterpart N₂.

The circuit configuration from the pair of input terminals 1 and 2 tothe primary winding N₁ of the transformer 5 of the FIG. 9 embodiment isakin to that of FIG. 8. The d.c.-to-d.c. converter circuit including thesecond main switch Q₂ in this FIG. 9 embodiment is similar to theforward converter circuit of 7. The rectifying and smoothing circuit 6_(a) and transformer secondary N_(2a) are therefore analogous inconstruction and operation with those designated by the same referencecharacters in FIG. 6. The main inductor L₁ and second ancillary inductorL_(a) of FIG. 9 are the same in construction and connections as those ofFIG. 8. The two main switches Q₁ and Q₂ and one ancillary switch Q₃ ofFIG. 9 are controlled just like their FIG. 6 counterparts. Consequently,the same voltage and current waveforms as those given in FIG. 7 appearin the FIG. 9 embodiment. The operation of this embodiment willtherefore be described with reference to FIG. 7.

From t₂ to t₃ in FIG. 7, when the ancillary switch Q₃ is conductive asat (C) in this figure, the current I_(da) will flow as at (K) in FIG. 7along the path comprising the first rectifier output 43, first ancillaryinductor L_(a), first reverse-blocking diode D_(a), ancillary switch Q₃,and second rectifier output 44. At the same time the current I_(db) willalso flow as at (L) in FIG. 7 along the path comprising the smoothingcapacitor C₁, transformer primary N₁, second ancillary inductor L_(b),second reverse-blocking diode D_(b), and ancillary switch Q₃.

Energy release from the main inductor L₁ continues in this t₂-t₃ period,as before t₂. This energy release will cause the current I_(d1) to flowto the smoothing capacitor C₁ via the rectifying diode D₁, as at (M) inFIG. 7, and the current I_(da) to flow to the first ancillary inductorL_(a), as at (K) in FIG. 7. As a result, in this FIG. 9 embodiment too,the current I_(d1) through the rectifying diode D₁ will decrease inmagnitude more rapidly than before upon conduction of the ancillaryswitch Q₃, as at (M) in FIG. 7.

The voltage V_(q2) across the second main switch Q₂ will dropapproximately to zero by resonance during the t₂-t₃ period, as in theFIG. 1 embodiment. The first soft-switching capacitor C_(q1) will beunclamped from the voltage V_(c1) across the smoothing capacitor C₁ att₄ when the rectifying diode D₁ becomes nonconductive. Resonance currentwill flow during the ensuing t₄-t₅ period along the path comprising thefirst soft-switching capacitor C_(q1), main inductor L₁, first ancillaryinductor L_(a), first reverse-blocking diode D_(a), and ancillary switchQ₃. Energy transfer will thus occur from first soft-switching capacitorC_(q1) to first ancillary inductor L_(a). The voltage V_(q1) across thefirst soft-switching capacitor C_(q1) and first main switch Q₁ will dropto zero at t₅. The two main switches Q₁ and Q₂ may therefore be turnedon at zero voltage at t₅ or at any moment from t₅ to t₆.

Embodiment of FIG. 10

The FIG. 10 embodiment is identical with that of FIG. 1 except that thesecond ancillary inductor L_(b) is connected to a junction P₃ betweentransformer primary N₁ and smoothing capacitor C₁, instead of to thejunction P₂ between transformer primary N₁ and second main switch Q₂ asin FIG. 1. This embodiment is therefore similar in operation to that ofFIG. 1 except for a slight difference in the flow path of the currentI_(db) through the reverse-blocking diode D_(b).

The operation of the FIG. 10 embodiment will be best understood byreferring to FIG. 5 again. From t₁ to t₇ in this figure, current willflow along the path comprising the smoothing capacitor C₁, secondancillary inductor L_(b), second reverse-blocking diode D_(b), andancillary switch Q₃. Current will also flow from t₂ to t₃ along the pathcomprising the second soft-switching capacitor C_(q2), transformerprimary N₁, second ancillary inductor L_(b), second reverse-blockingdiode D_(b), and ancillary switch Q₃. Current will also flow from t₃ tot₇ along the path comprising the second ancillary inductor L_(b), secondreverse-blocking diode D_(b), ancillary switch Q₃, second parallel diodeD_(q2), and transformer primary N₁. In this FIG. 10 power supply, too,the voltage V_(q2) across the second main switch Q₂ will diminish fromt₂ to t₃ by reason of the resonance of the second soft-switchingcapacitor C_(q2) and second ancillary inductor L_(b). The second mainswitch Q₂ may therefore be turned on at zero voltage after t₃ in FIG. 5.

As an additional modification of the FIG. 10 embodiment, the secondancillary inductor L_(b) may have one extremity thereof connected to atap P₄ on the transformer primary N₁, as indicated by the broken line inFIG. 10, instead of to the junction P₃. The resonance due to the secondsoft-switching capacitor C_(q2) and the second ancillary inductor L_(b)will then occur just as when the second ancillary inductor L_(b) isconnected to the junction P₃.

Embodiment of FIG. 11

The FIG. 11 embodiment is identical with that of FIG. 6 except that thesecond ancillary inductor L_(b) has one of its opposite extremitiescoupled to the junction P₃ between transformer primary N₁ and smoothingcapacitor C₁, instead of to the junction between transformer primary N₁and second main switch Q₂. The relationship between transformer primaryN₁ and second ancillary inductor L_(b) in FIG. 11 is analogous with thatin FIG. 10, so that current will flow through the second ancillaryinductor L_(b) and second reverse-blocking diode D_(b) in FIG. 11 alongthe same paths as in FIG. 10. Thus the FIG. 11 embodiment wins the sameadvantages as does that of FIG. 6. Incidentally, in this FIG. 11embodiment too, the second ancillary inductor L_(b) could be connectedto a tap P₄ on the transformer primary N₁.

Embodiment of FIG. 12

The FIG. 12 embodiment is identical with that of FIG. 8 except that thesecond ancillary inductor L_(b) has one of its opposite extremitiescoupled to the junction P₃ between transformer primary N₁ and smoothingcapacitor C₁, instead of to the junction between transformer primary N₁and second main switch Q₂. The relationship between transformer primaryN₁ and second ancillary inductor L_(b) in FIG. 12 is analogous with thatin FIG. 10, so that current will flow through the second ancillaryinductor L_(b) and second reverse-blocking diode D_(b) in FIG. 12 alongthe same paths as in FIG. 10. Thus the FIG. 12 embodiment wins the sameadvantages as does that of FIG. 8. In this FIG. 12 embodiment, too, thesecond ancillary inductor L_(b) could be connected to a tap P₄ on thetransformer primary N₁.

Embodiment of FIG. 13

The FIG. 13 embodiment is identical with that of FIG. 9 except that thesecond ancillary inductor L_(b) has one of its opposite extremitiescoupled to the junction P₃ between transformer primary N₁ and smoothingcapacitor C₁, instead of to the junction between transformer primary N₁and second main switch Q₂. The relationship between transformer primaryN₁ and second ancillary inductor L_(b) in FIG. 13 is analogous with thatin FIG. 10, so that current will flow through the second ancillaryinductor L_(b) and second reverse-blocking diode D_(b) in FIG. 13 alongthe same paths as in FIG. 10.

Embodiment of FIG. 14

In FIG. 14 is shown a modified switch control circuit 8 _(a) for use insubstitution for the first disclosed switch control circuit 8, FIG. 2,in any of the foregoing forms of switching power supplies according tothe invention. The modified switch control circuit 8 _(a) has two timers34 _(a) and 34 _(b), in place of the first timer 34 of the FIG. 2circuit, for differently limiting the conducting periods of the two mainswitches Q₁ and Q₂. The first timer 34 _(a) is connected betweenperiodic wave generator 29 and first AND gate 35. The second timer 34_(b) is connected between periodic wave generator 29 and second AND gate36. The modified switch control circuit 8 _(a) is similar to its FIG. 2counterpart 8 in all the other details of construction. What is labeled“third timer” and designated 37 in FIG. 14 is therefore equivalent tothe second timer bearing the same reference numeral in FIG. 2, puttingout the ancillary switch control signal V_(g3) for delivery over theconductor 19 to the gate of the ancillary switch Q₃.

FIG. 15 depicts the voltage waveforms appearing at various parts of theFIG. 14 switch control circuit 8 _(a), just as FIG. 3 does for the FIG.2 switch control circuit 8. The waveforms (A) through (E) in FIG. 15 areequivalent to those shown at (A) through (E) in FIG. 3. Seen at (F) inFIG. 15 are the “negative” output pulses V_(34a) of the first timer 34_(a) each having a first prescribed duration T_(1a), and at (G) the“negative” output pulses V_(34b) of the second timer 34 _(b) each havinga second prescribed duration T_(1b). Triggered by an output pulseV_(osc) of the unshown clock in the periodic wave generator 29, bothtimers 34 _(a) and 34 _(b) go low at t₀, but the second timer 34 _(b)goes back high at t₁′, earlier than t₁ when the first timer 34 _(a) doesso. However, these showings of FIG. 15 are by way of example only: Thefirst timer output pulses V_(34a), may be each shorter in duration thaneach second timer output pulse V_(34a).

The first AND gate 35 puts out the first main switch control signalV_(g1), FIG. 15(H), as the logical product of the output voltage V₃₀,FIG. 15 (C), of the comparator 30 and the output voltage V_(34a), FIG.15(F), of the first timer 34 _(a). The second AND gate 36 puts out thesecond main switch control signal V_(g2), FIG. 15(I), as the logicalproduce of the output voltage V₃₃, FIG. 15(E), of the comparator 33 andthe output voltage V_(34b). FIG. 15(G), of the second timer 34 _(b). Theancillary switch control signal V_(g3), FIG. 15(J), for the ancillaryswitches Q₃ is produced by the third timer 37 as in FIGS. 2 and 3.

Thus the modified switch control circuit 8 _(a) drives the two mainswitches Q₁ and Q₂ at the same frequency but initiates conductiontherethrough at different moments. This is apparent from (H) and (I) inFIG. 15 where the main switch control signals V_(g1) and V_(g2) areshown to rise at different moments. Conduction may indeed be initiatedthrough the two main switches Q₁ and Q₂ at any desired moments relativeto each other by the timers 34 _(a) and 34 _(b).

Embodiment of FIGS. 16-19

In the FIG. 16 embodiment is incorporated another modified switchcontrol circuit 8 _(b) which differs from its FIG. 1 counterpart inhaving two additional input conductors 38 and 39 connected thereto. Theinput conductor 38 is connected to the drain of the first main switch Q₁for detection of the voltage across the same. The other input conductor39 is connected to the drain of the second main switch Q₂ for detectionof the voltage across the same.

As shown in detail in FIG. 17, the switch control circuit 8 _(b) has twolow-voltage detector circuits 51 and 52 in places of the timers 34 _(a)and 34 _(b) of the FIG. 14 switch control circuit 8 _(a). The firstlow-voltage detector circuit 51 is connected by way of the additionalinput conductor 38 to the drain of the first main switch Q₁, FIG. 16,for ascertaining whether the drain-source voltage of the first mainswitch is less than a first reference voltage V_(a) or not. The secondlow-voltage detector circuit 52 is connected by way of the otheradditional input conductor 39 to the drain of the second main switch Q₂for determining whether drain-source voltage of the second main switchis less than a second reference voltage V_(b) or not. Both low-voltagedetector circuits 51 and 52 have additional inputs connected to theclock output 29 _(b) of the period wave generator 29 in order to detectthe drain-source voltages of the main switches Q₁ and Q₂ in synchronismwith the sawtooth voltage V_(t).

The low-voltage detector circuits 51 and 52 have their outputs connectedto the AND gates 35 and 36, respectively. The output voltages V₅₁ andV₅₂ of the low-voltage detector circuits 51 and 52 function like theoutputs 34 _(a) and 34 _(b) of the timers 34 _(a) and 34 _(b) of theFIG. 14 switch control circuit 8 _(a), as will become more apparent asthe description proceeds.

FIG. 18 is a detailed illustration of both low-voltage detector circuits51 and 52. The following description of this figure will be betterunderstood when taken together with FIG. 19, a diagram of voltagewaveforms appearing in the FIG. 18 circuitry. The first low-voltagedetector circuit 51 includes a comparator 53 having a negative inputconnected to the drain of the first main switch Q₁ via the inputconductor 38, and a positive input connected to a reference voltagesource 54. As indicated at (A) in FIG. 19, the first reference voltageV_(a) from the source 54 is less than the maximum value, and somewhatmore than the minimum value, of the drain-source voltage V_(q1) of thefirst main switch Q₁. The output V₅₃ from the comparator 53 is thereforehigh, as at (C) in FIG. 19, when the voltage V_(q1) across the firstmain switch Q₁ is less than the first reference voltage V_(a), as fromt₂ to t₃ in FIG. 19.

Connected to the output of the comparator 53, a trigger circuit 55 putsout a trigger pulse V₅₅, FIG. 19(E), when the comparator output V₅₃ goeshigh as at t₂. A flip-flop 56, the final-stage component of the firstlow-voltage detector circuit 51, has a set input S connected to thetrigger circuit 55, a reset input R connected to the clock output 29_(b) of the periodic wave generator 29, and a noninverting output Qconnected to the AND gate 35, FIG. 17. Reset as at t₀ in FIG. 19 by eachclock pulse V_(osc), FIG. 19(G), the flip-flop 56 will provide an outputV₅₁, FIG. 19(H), which will be low until t₂ when it is set by the highoutput V₅₅ from the trigger circuit 55. This output V₅₁, is delivered asaforesaid to the AND gate 35, FIG. 17, together with the output V₃₀ fromthe first main switch control circuit 61.

The second low-voltage detector circuit 52 includes a comparator 57having a negative input connected to the drain of the second main switchQ₂ via the input conductor 39, and a positive input connected to areference voltage source 58. As indicated at (B) in FIG. 19, the firstreference voltage V_(b) from its source 58 is less than the maximumvalue, and somewhat more than the minimum value, of the drain-sourcevoltage V_(q2) of the second main switch Q₂. The output V₅₇ from thecomparator 57 is therefore high, as at (D) in FIG. 19, when the voltageV_(q2) across the second main switch Q₂ is less than the secondreference voltage V_(b), as from t₁ to t₄ in FIG. 19.

Connected to the output of the comparator 57, a trigger circuit 59 putsout a trigger pulse V₅₉, FIG. 19(F), when the comparator output V₅₇ goeshigh as at t₁. A flip-flop 60, the final-stage component of the secondlow-voltage detector circuit 52, has a set input S connected to thetrigger circuit 59, a reset input R connected to the clock output 29_(b) of the periodic wave generator 29, and a noninverting output Qconnected to the AND gate 36, FIG. 17. Reset as at t₀ in FIG. 19 by eachclock pulse V_(osc), FIG. 19(G), the flip-flop 60 will provide an outputV₅₂, FIG. 19(I), which will be low until t₁ when it is set by the highoutput V₅₉ from the trigger circuit 59. This output V₅₂ is delivered tothe AND gate 36, FIG. 17, together with the output V₃₃ from the secondmain switch control circuit 62.

Although the reference voltages V_(a) and V_(b) are shown higher thanzero at (A) and (B) in FIG. 19, these reference voltages could be zeroin cases where noise production is no problem. Further the referencevoltages V_(a)and V_(b) could be either the same or different.

The moment t₂ when the output V₅₁ from the first low-voltage detectorcircuit 51 goes high, as at(H) in FIG. 19, represents the moment whenthe low- or zero-voltage switching of the first main switch Q₁ becomespossible. Similarly, the moment ti when the output V₅₂ from the secondlow-voltage detector circuit 52 goes high, as at (I) in FIG. 19,represents the moment when the low- or zero-voltage switching of thesecond main switch Q₂ becomes possible. Thus the low-voltage detectorcircuits 51 and 52 of the FIG. 17 switch control circuit 8 _(b) performthe same functions as the timers 34 _(a) and 34 _(b) of the FIG. 14switch control circuit 8 _(a), conducing to the soft-switching of thetwo main switches Q₁ and Q₂.

The main switches Q_(q) and Q₂ of this FIG. 16 embodiment are turned onwhen their voltages V_(q1) and V_(q2) drop below the reference voltagesV_(a) and V_(b), respectively, as a result of soft switching. Morestable soft-switching of the main switches Q₁ and Q₂ is thereforepossible by this switch control circuit 8 _(b) than by its FIG. 2counterpart 8 or FIG. 14 counterpart 8 _(a). For, in use of the timer 34of the FIG. 2 switch control circuit 8, or of the timers 34 _(a) and 34_(b) of the FIG. 14 circuit 8 _(a), the main switches Q₁ and Q₂ will bealmost unavoidably subject to fluctuations in the moments when they areturned on, because of errors in the durations of the output pulses ofthose timers. This switch control circuit 8 _(b) lends itself to use notonly in the FIG. 1 embodiment but in those of FIGS. 6, 8-11, 13 and 14as well.

Possible Modifications

Notwithstanding the foregoing detailed disclosure it is not desired thatthe present invention be limited by the exact showing of the drawings orthe description thereof. The following is a brief list of possiblemodifications of the illustrated embodiments:

1. The main switches Q₁ and Q₂ could be made bidirectional, in whichcase the parallel diodes D_(q1) and D_(q2) would be unnecessary.

2. An insulated-gate bipolar transistor or any other suitablesemiconductor switches could be used in place of the FET switches Q₁,Q₂and Q₃.

3. The periodic wave generator 29 is so named because a triangular wavecould be employed in lieu of a sawtooth wave.

4. The AND gates 35 and 36 of the switch control circuits 8, 8 _(a)and 8_(b) could be replaced by other essentially equivalent logic circuits.

5. The current detector circuit 9 could be connected on the input sideof the rectifier circuit 4.

6. The voltage detecting conductor 21 could also be connected on theinput side of the rectifier circuit 4 via an other rectifier circuit.

7. The first reverse-blocking diode D_(a) could be connected on theinput side of the first ancillary inductor L_(a).

8. The second reverse-blocking diode D_(b) could be connected betweensecond ancillary inductor L_(b) and transformer primary N₁.

What is claimed is:
 1. A switching power supply capable of translatinga.c. voltage of sinusoidal waveform into d.c. voltage, comprising: (a) apair of a.c. input terminals for inputting a.c. voltage having a knownfrequency; (b) a rectifier circuit connected to the pair of inputterminals for rectifying the input a.c. voltage, the rectifier circuithaving a first and a second output for providing a rectifier outputvoltage; (c) a main inductor connected to the first output of therectifier circuit; (d) a first main switch connected to the first outputof the rectifier circuit via the main inductor on one hand and, on theother hand, to the second output of the rectifier circuit; (e) firstsoft-switching capacitance means associated with the first main switch;(f) a rectifying diode; (g) a smoothing capacitor connected in parallelwith the main switch via the rectifying diode and having a firstterminal and a second terminal; (h) a transformer; (i) a second mainswitch connected to the first terminal of the smoothing capacitor via aprimary winding of the transformer on one hand and, on the other hand,to the second terminal of the smoothing capacitor; (j) secondsoft-switching capacitance means associated with the second main switch;(k) a rectifying and smoothing circuit connected to the transformer forproviding output d.c. voltage; (l) a first ancillary inductor connectedto the main inductor and electromagnetically coupled thereto; (m) anancillary switch connected to the main inductor via the first ancillaryinductor on one hand and, on the other hand, to the second output of therectifier circuit; (n) a first reverse-blocking diode connected inseries with the first ancillary inductor; (o) a second ancillaryinductor electromagnetically coupled to the primary winding of thetransformer and having one extremity connected to a junction between thesecond main switch and the smoothing capacitor, and another extremityconnected to the ancillary switch; (p) a second reverse-blocking diodeconnected in series with the second ancillary inductor; and (q) a switchcontrol circuit connected to the first main switch for on-off controlthereof at a repetition frequency higher than the frequency of the inputa.c. voltage, to the second main switch for on-off control thereof inorder to cause d.c. voltage to be intermittently applied from thesmoothing capacitor to the primary winding of the transformer, and tothe ancillary switch for on-off control thereof at such a repetitionfrequency, and with such conducting periods, as to assure soft turn-onof the first and the second main switch.
 2. The switching power supplyof claim 1 wherein the switch control circuit is adapted to drive thefirst and the second main switch at the same repetition frequency. 3.The switching power supply of claim 2 wherein the switch control circuitis adapted to turn the first and the second main switch at the samemoment.
 4. The switching power supply of claim 1 wherein the switchcontrol circuit comprises: (a) first voltage detector means fordetecting an input voltage or an output voltage of the rectifiercircuit; (b) second voltage detector means for detecting a voltageacross the smoothing capacitor; (c) third voltage detector means fordetecting the output voltage of the rectifying and smoothing circuit;(d) current detector means for detecting a current through the rectifiercircuit; (e) a periodic wave generator for generating a periodic voltagewave with a frequency higher than the frequency of the input a.c.voltage; (f) first tentative conducting period determination meansconnected to the first and the second voltage detector means and thecurrent detector means and the periodic wave generator for determiningtentative conducting periods for the first main switch in order to holdthe voltage across the smoothing capacitor at a desired value and tocause the input current of the rectifier circuit to approximate asinusoidal waveform; (g) second tentative conducting perioddetermination means connected to the third voltage detector means andthe periodic wave generator for determining tentative conducting periodsfor the second main switch in order to hold the output voltage of therectifying and smoothing circuit at a desired value; (h) a timerconnected to the periodic wave generator for determining conductingperiods for the ancillary switch in synchronism with the periodic wave;(i) conducting period limitation means for providing a conducting periodlimitation signal that is in a prescribed state for a prescribed periodof time from the beginning of each conducting period of the ancillaryswitch; (j) a first logic circuit having inputs connected to the firsttentative conducting period determination means and the conductingperiod limitation means for nullifying the tentative conductive periodsfor the first main switch as long as the conducting period limitationsignal is in the prescribed state; and (k) a second logic circuit havinginputs connected to the second tentative conducting period determinationmeans and the conducting period limitation means for nullifying thetentative conductive periods for the second main switch as long as theconducting period limitation signal is in the prescribed state.
 5. Theswitching power supply of claim 4 wherein the conducting periodlimitation means comprises a timer connected to the periodic wavegenerator for providing the conducting period limitation signal insynchronism with the periodic wave.
 6. The switching power supply ofclaim 1 wherein the switch control circuit comprises: (a) first voltagedetector means for detecting an input voltage or an output voltage ofthe rectifier circuit; (b) second voltage detector means for detecting avoltage across the smoothing capacitor; (c) third voltage detector meansfor detecting the output voltage of the rectifying and smoothingcircuit; (d) current detector means for detecting a current through therectifier circuit; (e) a periodic wave generator for generating aperiodic voltage wave with a frequency higher than the frequency of theinput a.c. voltage; (f) first tentative conducting period determinationmeans connected to the first and the second voltage detector means andthe current detector means and the periodic wave generator fordetermining tentative conducting periods for the first main switch inorder to hold the voltage across the smoothing capacitor at a desiredvalue and to cause the input current of the rectifier circuit toapproximate a sinusoidal waveform; (g) second tentative conductingperiod determination means connected to the third voltage detector meansand the periodic wave generator for determining tentative conductingperiods for the second main switch in order to hold the output voltageof the rectifying and smoothing circuit at a desired value; (h) a timerconnected to the periodic wave generator for determining conductingperiods for the ancillary switch in synchronism with the periodic wave;(i) first conducting period limitation means for providing a firstconducting period limitation signal that is in a prescribed state for afirst prescribed period of time from the beginning of each conductingperiod of the ancillary switch; (j) second conducting period limitationmeans for providing a second conducting period limitation signal that isin a prescribed state for a second prescribed period of time from thebeginning of each conducting period of the ancillary switch; (k) a firstlogic circuit having inputs connected to the first tentative conductingperiod determination means and the first conducting period limitationmeans for nullifying the tentative conductive periods for the first mainswitch as long as the first conducting period limitation signal is inthe prescribed state; and (l) a second logic circuit having inputsconnected to the second tentative conducting period determination meansand the second conducting period limitation means for nullifying thetentative conductive periods for the second main switch as long as thesecond conducting period limitation signal is in the prescribed state.7. The switching power supply of claim 6 wherein the first conductingperiod limitation means comprises a timer connected to the periodic wavegenerator for providing the first conducting period limitation signal insynchronism with the periodic wave, and wherein the second conductingperiod limitation means comprises another timer connected to theperiodic wave generator for providing the second conducting periodlimitation signal in synchronism with the period wave.
 8. The switchingpower supply of claim 1 wherein the switch control circuit comprises:(a) first voltage detector means for detecting an input voltage or anoutput voltage of the rectifier circuit; (b) second voltage detectormeans for detecting a voltage across the smoothing capacitor; (c) thirdvoltage detector means for detecting the output voltage of therectifying and smoothing circuit; (d) current detector means fordetecting a current through the rectifier circuit; (e) a periodic wavegenerator for generating a periodic voltage wave with a frequency higherthan the frequency of the input a.c. voltage; (f) first tentativeconducting period determination means connected to the first and thesecond voltage detector means and the current detector means and theperiodic wave generator for determining tentative conducting periods forthe first main switch in order to hold the voltage across the smoothingcapacitor at a desired value and to cause the input current of therectifier circuit to approximate a sinusoidal waveform; (g) secondtentative conducting period determination means connected to the thirdvoltage detector means and the periodic wave generator for determiningtentative conducting periods for the second main switch in order to holdthe output voltage of the rectifying and smoothing circuit at a desiredvalue; (h) a timer connected to the periodic wave generator fordetermining conducting periods for the ancillary switch in synchronismwith the periodic wave; (i) first main switch voltage detector means fordetecting voltage across the first main switch; (j) second main switchvoltage detector means for detecting voltage across the second mainswitch; (k) means for providing a first and a second reference voltage;(l) a first comparator connected to the first main switch voltagedetector means and to the providing means for comparing the voltageacross the first main switch with the first reference voltage; (m) asecond comparator connected to the second main switch voltage detectormeans and to the providing means for comparing the voltage across thesecond main switch with the second reference voltage; (n) firstconducting period limitation means connected to the first comparator forproviding a first conducting period limitation signal that is in aprescribed state from the beginning of each conducting period of theancillary switch to the moment when the voltage across the first mainswitch becomes less than the first reference voltage; (o) secondconducting period limitation means connected to the second comparatorfor providing a second conducting period limitation signal that is in aprescribed state from the beginning of each conducting period of theancillary switch to the moment when the voltage across the second mainswitch becomes less than the second reference voltage; (p) a first logiccircuit having inputs connected to the first tentative conducting perioddetermination means and the first conducting period limitation means fornullifying the tentative conductive periods for the first main switch aslong as the first conducting period limitation signal is in theprescribed state; and (q) a second logic circuit having inputs connectedto the second tentative conducting period determination means and thesecond conducting period limitation means for nullifying the tentativeconductive periods for the second main switch as long as the secondconducting period limitation signal is in the prescribed state.
 9. Theswitching power supply of claim 1 wherein the transformer has asecondary winding, and wherein the rectifying and smoothing circuit isconnected to the secondary winding of the transformer.
 10. The switchingpower supply of claim 9 wherein the rectifying and smoothing circuitcomprises: (a) a rectifying diode connected to one extremity of thesecondary winding of the transformer, the rectifying diode being sooriented as to become conductive in response to a voltage developingacross the transformer secondary during the nonconducting periods of thesecond main switch; and (b) a smoothing capacitor connected in parallelwith the transformer secondary via the rectifying diode.
 11. Theswitching power supply of claim 9 wherein the rectifying and smoothingcircuit comprises: (a) a rectifying diode connected to one extremity ofthe secondary winding of the transformer, the rectifying diode being sooriented as to become conductive in response to a voltage developingacross the transformer secondary during the conducting periods of thesecond main switch; and (b) a smoothing circuit connected in parallelwith the transformer secondary via the rectifying diode.